Junior Digital Design Engineer - RTL, DFT & SOC Subsystems

Experteer Italy is looking for a professional to lead the Analog Layout team in Catania, Italy, focusing on delivering high-performance MCU and ICs. The role involves collaboration with mixed-signal and software teams to ensure optimized system performance and product quality. Candidates should have a Bachelor's or Master's degree in Electrical Engineering and strong expertise in Verilog/SystemVerilog. This position offers a challenging environment with opportunities for impact in cutting-edge projects. #J-18808-Ljbffr