Descrizione:
Overview
In this role you will define and deliver SerDes and clocking IP for high-speed, power-efficient interconnects, shaping next-generation semiconductor solutions. You will collaborate with digital, layout and verification teams across the full development cycle to translate architectures into robust analog blocks. You will own verification planning and support silicon bring-up through release, contributing to a scalable high-speed design platform. This opportunity combines hands-on analog design with system-level insight in a dynamic, innovation-driven environment near Milan.
Benefits
- Define, analyse and refine SerDes architectures with the engineering group
- Design key analog IP blocks (PLLs, DLLs, amplifiers, samplers, equalisation circuits)
- Develop supporting analog functions (bias circuits, regulators, ADCs, DACs)
- Lead verification planning and support silicon bring-up through release
Responsibilities
- 5+ years of relevant industry experience with a suitable technical degree
- Strong hands-on SerDes design experience in advanced FinFET CMOS nodes
- Proficient with Cadence, Spectre and Calibre
- Solid grounding in analog IC design with understanding of signal integrity and power integrity
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