Analog IC Design Engineer – SerDes, High Speed, PLL

Analog IC Design Engineer – SerDes, High Speed, PLL I am recruiting for a Senior Analog IC Design Engineer for my client near Milan, a company developing high-speed data communication silicon using advanced CMOS process technologies.

As a Senior Analog IC Design Engineer, you will play a key role in defining and delivering critical SerDes and clocking IP used in power-efficient interconnect solutions. The Senior Analog IC Design Engineer will work closely with digital, layout and verification engineers through the full development cycle.

Responsibilities

Define, analyse and refine SerDes architectures in collaboration with the wider engineering group

Design key analog IP blocks such as PLLs, DLLs, amplifiers, samplers and equalisation circuits

Develop supporting analog functions including bias circuits, regulators, ADCs and DACs

Lead verification planning and support silicon bring-up through to release

Requirements

5+ years of relevant industry experience with a suitable technical degree

Strong hands on experience in SerDes design in advanced FinFET CMOS nodes

Confident use of industry standard EDA tools including Cadence, Spectre and Calibre

Solid grounding in analog IC design with good understanding of signal integrity and power integrity

This opportunity suits a Senior Analog IC Design Engineer looking for challenging high-speed design work.

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