Lead Staff Verification Engineer - SystemVerilog/UVM

Analog Devices in Assago, Italy is seeking a Staff Design Verification Engineer to join their Data Center and Energy group. The successful candidate will have a strong track record in verifying complex mixed/digital signals ICs and will focus on verification methodologies for Power Conversion solutions.

This role requires expertise in Verilog, System Verilog, and UVM, alongside a Bachelor’s or Master’s degree in Electronics Engineering with at least 8 years of relevant experience.

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