Principal analog design and verification engineer (f/m/div)

Principal Analog Design and Verification Engineer – Research & Development We are looking for a seasoned analog design and verification engineer to lead verification efforts for high‑speed Ser Des building blocks and systems. Key Responsibilities Perform analog‑centric verification of high‑speed Ser Des building blocks, including voltage- and current‑mode drivers, de‑/serializers, CTLE, VGA, slicers, and phase interpolators. Conduct high‑sigma verification to ensure robustness and reliability of high‑speed Ser Des building blocks. Lead analog‑centric top‑level verification of high‑speed Ser Des systems, covering key scenarios such as start‑up, power‑down, and IR‑drop analysis. Execute Analog‑Mixed Signal Verification of high‑speed Ser Des building blocks such as clock‑and‑data recovery, continuous‑time linear equalization (CTLE), adaptive channel equalization (FFE/DFE), and sampler offset compensation. Qualifications 10+ years of experience in high‑speed analog‑centric mixed‑signal verification. Strong expertise in high‑speed Ser Des concepts, including CDR, CTLE, FFE/DFE, and sampler offset compensation. In‑depth knowledge of Ser Des building blocks such as voltage‑ and current‑mode drivers, de‑/serializers, CTLE, VGA, slicers, and phase interpolators. Proven experience with analog and analog/mixed‑signal simulation tools. Previous experience as an analog designer is considered a strong advantage. Fluency in English (mandatory). Compensation Indicative Salary Range: 57,600 € – 79,200 € (Pavia, Italy). We embrace diversity and inclusion. All qualified applicants are encouraged to apply. #J-18808-Ljbffr