Principal Physical Digital Design Engineer

Principal Physical Design Engineer

The Chips-IT Foundation is expanding its microelectronics design team and is seeking a highly experienced Principal Physical Design Engineer to play a key technical leadership role in advanced System-\u2011on-\u2011Chip (SoC) development programs. The position will contribute to cutting-\u2011edge R&D activities, working closely with architecture, RTL, verification, and technology teams in a state-\u2011of-\u2011the-\u2011art microelectronics design environment. The Principal Physical Design Engineer will be responsible for leading and executing complex digital design flows for advanced semiconductor nodes. The role requires deep hands-\u2011on expertise across the full physical implementation lifecycle, from netlist handoff through place & route, signoff, and tape-\u2011out, while also providing technical mentorship and driving best practices within the design team. The work can be carried out either in Pavia or in Bologna.

Key Responsibilities

• Lead and execute end-\u2011to-\u2011end physical design flows for complex SoCs and IP blocks, from RTL handoff to GDSII.
• Collaborate closely with RTL, verification, DFT, and architecture teams to resolve design and implementation issues.
• Work with PDKs and technology teams to ensure correct usage of advanced-\u2011node design rules and constraints.
• Develop, document, and improve physical design methodologies, scripts, and automation flows.
• Mentor junior engineers and provide technical leadership across physical design activities.

Requirements

• Master’s degree (or PhD) in Electrical Engineering, Computer Engineering, or a related field.
• Extensive hands-\u2011on experience in physical design for advanced technology nodes (e.g., 16\u00a0nm and below).
• Strong expertise with industry-\u2011standard EDA tools (Cadence, Synopsys, Siemens).
• Solid understanding of semiconductor fabrication processes and foundry design requirements.
• Proficiency in Tcl, Python, or Perl for flow automation and methodology development.
• Experience supporting multiple tape-\u2011outs in advanced nodes.

Benefits

• Competitive compensation and contract type, negotiated based on qualifications and experience.
• Possibility to enter into a PhD program that grants the PhD title.
• Lunch tickets.
• Private health care coverage, depending on the role and contract.
• Structured growth path, with ongoing access to training and updates.
• Networking opportunities with industry-\u2011leading professionals.
• International work environment.
• Hybrid work policy.
• Tax deductions: Eligible candidates from abroad, comprising Italian citizens, who have carried scientific research activity abroad and meet specific requirements, may be entitled to a taxable income deduction up to 90% for a period of 6 to 13 years.

In conformità con le normative vigenti, il range retributivo lordo annuo previsto per questa posizione è compreso tra €25.000,00 e €55.000,00. L'ampiezza del range è finalizzata a valutare candidature con diversi livelli di seniority; l'offerta finale sarà strettamente commisurata all'effettiva esperienza e alle competenze del candidato, e sarà integrata dai benefit aziendali previsti per il ruolo.

#J-18808-Ljbffr