Senior MEMS Analog Mixed-Signal Verification Lead

Experteer Italy in Agrate Brianza is seeking a professional to validate mixed-signal ASICs in the MEMS group. You will define and develop verification test benches and collaborate across teams to ensure robust silicon for cutting-edge applications. The ideal candidate has 3-5 years in ASIC verification, knowledge of analog design, and familiarity with SystemVerilog and Cadence tools. Fluency in English and good communication skills are essential.

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